summaryrefslogtreecommitdiff
path: root/src/database/apple_cpu_fallback.hpp
diff options
context:
space:
mode:
authorCedric Nugteren <web@cedricnugteren.nl>2018-03-15 20:58:42 +0100
committerCedric Nugteren <web@cedricnugteren.nl>2018-03-15 20:58:42 +0100
commit7a756cbce7e3e025ec9fbadd717a32d4711262ad (patch)
tree292cef2b032079d31e5f6cf5fd804bb7ee4110e6 /src/database/apple_cpu_fallback.hpp
parentf4d96e80c385404a59a17588386d4115fd0bef6b (diff)
Fixed a failing TRSV test using a CPU with Apple OpenCL
Diffstat (limited to 'src/database/apple_cpu_fallback.hpp')
-rw-r--r--src/database/apple_cpu_fallback.hpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/database/apple_cpu_fallback.hpp b/src/database/apple_cpu_fallback.hpp
index e1aa4661..8d257b5e 100644
--- a/src/database/apple_cpu_fallback.hpp
+++ b/src/database/apple_cpu_fallback.hpp
@@ -41,7 +41,7 @@ const DatabaseEntry XgerApple = {
"Xger", Precision::kAny, {"WGS1", "WGS2", "WPT"}, { { kDeviceTypeAll, "default", { { "default", { { kDeviceNameDefault, Params{ 64, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } } } } }
};
const DatabaseEntry XtrsvApple = {
- "Xtrsv", Precision::kAny, {"TRSV_BLOCK_SIZE"}, { { kDeviceTypeAll, "default", { { "default", { { kDeviceNameDefault, Params{ 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } } } } }
+ "Xtrsv", Precision::kAny, {"TRSV_BLOCK_SIZE"}, { { kDeviceTypeAll, "default", { { "default", { { kDeviceNameDefault, Params{ 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } } } } }
};
const DatabaseEntry XgemmApple = {
"Xgemm", Precision::kAny, {"KWG", "KWI", "MDIMA", "MDIMC", "MWG", "NDIMB", "NDIMC", "NWG", "SA", "SB", "STRM", "STRN", "VWM", "VWN"}, { { kDeviceTypeAll, "default", { { "default", { { kDeviceNameDefault, Params{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1 } } } } } } }