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author | Cedric Nugteren <web@cedricnugteren.nl> | 2023-01-22 15:52:49 +0100 |
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committer | GitHub <noreply@github.com> | 2023-01-22 15:52:49 +0100 |
commit | ab5092dd26a3f95e57c3fba3be8315c024c72eed (patch) | |
tree | 369b50d015c70a02cfcec5ef16b0a8d0112342c1 /src/database/kernels/trsv_routine/trsv_routine_3232.hpp | |
parent | e72f87ae5eca5e2ea8aea4f2ce49408c1faa0521 (diff) | |
parent | c9856758b3c83c53a1185f848f23b55de1c9a2cc (diff) |
Merge pull request #452 from CNugteren/add_tuning_results_adreno
Add tuning results for 4 devies
Diffstat (limited to 'src/database/kernels/trsv_routine/trsv_routine_3232.hpp')
-rw-r--r-- | src/database/kernels/trsv_routine/trsv_routine_3232.hpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/database/kernels/trsv_routine/trsv_routine_3232.hpp b/src/database/kernels/trsv_routine/trsv_routine_3232.hpp index 171516f7..55328375 100644 --- a/src/database/kernels/trsv_routine/trsv_routine_3232.hpp +++ b/src/database/kernels/trsv_routine/trsv_routine_3232.hpp @@ -15,6 +15,7 @@ const DatabaseEntry TrsvRoutineComplexSingle = { { // AMD GPUs kDeviceTypeGPU, "AMD", { { "default", { + { Name{"AMD Radeon Pro 450 Compute Engine "}, Params{ 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { kDeviceNameDefault , Params{ 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, } }, { "gfx1030", { @@ -47,6 +48,14 @@ const DatabaseEntry TrsvRoutineComplexSingle = { } }, } }, + { // Intel accelerators + kDeviceTypeAccelerator, "Intel", { + { "default", { + { Name{"Intel(R) FPGA Emulation Device "}, Params{ 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { kDeviceNameDefault , Params{ 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + } }, + } + }, { // NVIDIA GPUs kDeviceTypeGPU, "NVIDIA", { { "SM6.0", { |